notes

key difference between IJTAG AND JTAG is

A typical implementation of an ICL ScanRegister consists of the following shift register, hold register(or latch) control logic retiming on the scan path

ICL modules building block keywords include ScanMux,ScanRegister ClockMux DataMux and DataRegister

Implicitly the scan register has the following signals enable test clock test reset and update enable

Tessent testKompress creates logic known as EDT logic

When using TestKompress less time is needed to simulate serial scan

The encoding capacity may be insufficient due to the decompressor logic size being too small

the number of test cubes values created being less than optimal

Boundary scan (Bscan) repeaters are components used in the boundary scan test architecture to extend the reach or improve the signal integrity of the test access port (TAP) signals across a printed circuit board (PCB) or between interconnected PCBs. In the context of the meeting, Vikram discussed an issue related to generating patterns for boundary scan testing, where additional pins needed to be controlled during the pattern generation. This issue was specific to the way patterns were generated in Braga, differing from the method used in Athena, due to the presence of additional ports in the JTAG chain that needed to be controlled but were not being allowed by the Tessent tool. Vikram mentioned that Tessent provided an alternate solution, which involved a lot of scripting to introspect the pattern spec and create separate test depths for each frame, indicating a complex workaround for handling boundary scan repeaters or similar components in the test chain.