scan insertion 2

The above graph shows set up violation.

The above figure is for hold violation. Hold violation is depended only on voltage not frequency.

The above are not functional error but performance issue

increase voltage fast , delay less, chips working then setup issue.

Increase frequency chips fail as delay less.

shift may require n clock cycle but cature only one clock cycle

In scan_en=0 only combo logic comes into play not wwhen scan_en =1

path when scan_en =1

By combining loading and unloading we can save number of clock cycles.

.synopsys_dc_setup has the libraries and scripts has the commands for scan insertion

link library all standard cells or library from tool generic

anything custom is target library

db files are synthesised by pd team or given by synopsys tool

simulation tool of synopsys is vcs

sdc standard design constraint is only for atpg for scan insertion all specification in tcl script

design compiler optimises designs to provide the smallest and fastest logical representation of a given function. it comprises tools that synthesize your hdl designs into optimized technology ependent gate level designs.it supports a wide range of flat and hierarchical design styles and can optimize both combinational and sequential designs for speed area and power.

design compiler uses technology libraries synthetic or designware libraries and symbol libraries to implement synthesis and to display synthesis results graphically.

after translating hdl description to gates design compiler optimises and maps the design to a specific technology library known as target library.

in delay test we need two vectors during capture mode. first one is normal. the second vector will be the output response of the combination block.each block will generate second vector for next stage. since there is no stage before the first one you need to force pi one more time. to capture the response for second vector we need to toggle system clock at real operating frequency. this is launch on capture.

in launch on shift u need high frequency scan en shift which is difficult

to select top level reset in scan mode test mode signal is used

if clk mixing is allowed then clock mux ( lock uplatch) in between two clk flip flop domains