scan insertion
synthesis gives gate level representation netlist by keeping in account power performance and area
LVT have high leakage but faster and HVT have low leakage but are slower.
LVT for high performance and HVT for high battery back up.
BIST JTAG BOUNDARY SCAN COMPRESSION OCC can be added at RTL but scan stitching can only happen at Netlist level since scan chain stitching needs flip flops. By adding test logic performance degraded due to delay so we go for incremental synthesis.In incremental synthesis we change from HVT to LVT and X2 to X4 higher drive strength to increase performance.
DFT we do structural testing not logical testing so ATPG patterns are different pre qual before scan insertion and after scan insertion.
Ad hoc dft
Minimizing redundant logic
Minimizing asynchronous logic
Isolating clocks from logic
Adding internal control and observation point
input-register (controllable), register-register(0 testability deep inside logic), register-output(observable), input-output(controllable and observable)
A testable circuit all internal nodes of interest can be set to logic 0 or 1 and any change in the desired logic value at a node of interest due to fault can be observed externally.
Multiple combinational blocks thats the whole concept of scan
post silicon we apply structural test which take veryless time than functional ATPG. So once we get 98 % of coverage is obtained by applying structural test vectors then we apply functional test vectors for remaining 2 % coverage.
Logical equivalent check
In normal/capture mode data input is selected to update the output.
In shift mode scan input is selected to update the output.
In normal/capture mode SE is set to 0. The value present in data input is captured into internal D flip flop.
In shift mode SE is set to 1.The SI is now used to shift in new data to the D flip flop while the content of D flip flop is shifted out.
shift operation takes place in edge triggered manner while capture operation takes place in level triggered manner.
Full scan design where all storage elements are converted to scan cells and combinationl ATPG is used for test generation and partial scan design where few storge elements are converted to scan cells and squential ATPG is used for test generation.
Scan verification is performed on both shift and capture operation in order to verify that expected response predicted by zero delay simulation used in test generation and fault simulation match with full timing behaviour
Stuck@ in partial scan
push fault effect value to nearest scannable flop.
this type of increasing capture pulse is called sequencial depth.
as long as you want capture scan enable should be low
The whole idea behind at speed testing is that if circuit works at 100 MHz and you want to test that are you getting the passed on value correct at 10 ns so you launch and 0 ns which is reference and capture at 10 ns.
Latch helps to avoid glitches ,either u want full clock or no clock . If you have half period clock dont pass it to ckt
dftmax generates decompressor and compactor
pl verification non timing simultion
tessent flow occ before synthesis in rtl
boundry scan uses T clk which is lower than the scan clk if scan clk is 100MHz T clk is 10MHz .
Why? because boundry is chip level and high frequency leads to heat and destroy the io
exclue pll port from jtag as we do not want glitch due to boundry scan to enter design set bsd-linkage is excluding
